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[Books] Hdl_examples.zip

Description: HDL参考例程 包括一些简单的fifo，adc，ram，uar，count的示例，
Platform: | Size: 232489 | Author: | Hits:

[Other resource] 一些VHDL源代码

Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45110 | Author: 蔡孟颖 | Hits:

[Other resource] my_ramlib_06

Description: 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL description, such as FIFO, Dual Port RAM, etc.
Platform: | Size: 616055 | Author: ruan | Hits:

[Other resource] vga.niosII.compent.v

Description: 在cyloneIIFPGA平台下设计完成测试通过的VGA控制器代码。显存留在系统的SDRAM中，用FIFO作为缓冲。-in cyloneIIFPGA platform design is completed tests through the VGA controller code. RAM in the system SDRAM, and use as a FIFO buffer.
Platform: | Size: 6599 | Author: Ray ZH | Hits:

[Embeded-SCM Develop] fifov1

Description: FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用 双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、 与写时钟同步的写有效（wren）和写数据（wr_data） 、与读时钟同步的读有效（rden）和读数据（rd_data） 为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和 满标志（full）以禁止读写操作。
Platform: | Size: 379609 | Author: lsg | Hits:

[Other resource] VHDL-ram_fifo

Description: VHDL的ram和fifo model code 包含众多的厂家
Platform: | Size: 1678507 | Author: SL | Hits:

[Embeded-SCM Develop] 通用存储器包括各种类型存储器的VHDL描述

Description: 通用存储器包括各种类型存储器的VHDL描述， 如FIFO，双口RAM等VHDL代码库
Platform: | Size: 617824 | Author: hanker3 | Hits:

[VHDL-FPGA-Verilog] ramFIFO

Description: 双口RAM实现FIFO程序解释,说明.-FIFO dual-port RAM procedures to achieve explanation. Good
Platform: | Size: 616448 | Author: nxl | Hits:

[Software Engineering] spartan6_fpga_blockram_user_guide

Description: Spartan6　FPGA中的块存储器使用指南，可以构建为FIFO，ROM，RAM，移位寄存器等。-Spartan6 FPGA block memory in the User Guide, you can build for FIFO, ROM, RAM, shift registers and so on.
Platform: | Size: 376832 | Author: james | Hits:

[Other] uart

Description: 此文档为C51单片机串口通讯学习程序（中断+FIFO)-This document is for the C51 microcontroller serial communication learning process (interrupted+ FIFO)
Platform: | Size: 6144 | Author: | Hits:

[assembly language] fifo_ram

Description: 同步fifo， 基于FPGA的VHDL编程，已调试。-fifo-ram
Platform: | Size: 1024 | Author: 曾馨月 | Hits:

[VHDL-FPGA-Verilog] RamFifoVHDL

Description: Ram Fifo Core VHDL file
Platform: | Size: 21504 | Author: Marcos Vinícius | Hits:

[VHDL-FPGA-Verilog] mypro_synfifo

Description: 基于IP核RAM的同步fifo设计，工程使用Xilinx的开发软件ISE-RAM-based synchronization fifo IP core design, engineering, software development using Xilinx ISE
Platform: | Size: 1275904 | Author: Hurley | Hits:

[VHDL-FPGA-Verilog] General-memory-VHDL-code-library

Description: 通用存储器VHDL代码库。fifo,ram寄存器的代码和测试模块。-General-purpose memory VHDL code base. fifo, ram register code and test modules.
Platform: | Size: 23552 | Author: 周鑫 | Hits:

[VHDL-FPGA-Verilog] FIFO-verilog

Description: 本实验完成的是8位异步FIFO的设计，其中写时钟100MHz,读时钟为5MHz，其中RAM的深度为256。当写时钟脉冲上升沿到来时，判断写信号是有效，则写一个八位数据到RAM中；当读时钟脉冲上升沿到来时，判断读信号是有效，则从RAM中把一个八位数据读出来。当RAM中数据写满时产生一个满标志，不能再往RAM再写数据；当RAM中数据读空时产生一个空标志，不能再从RAM读出数据。-In this study, completed the 8-bit asynchronous FIFO design, which write clock 100MHz, read clock is 5MHz, the depth of the RAM 256. When the rising edge of write clock pulse when writing the signal is valid, then write an eight-bit data to RAM when the rising edge of read clock pulse, the judge read the signal is valid, from eight bits of data in RAM to a read out. When RAM is full of data to generate a full mark, can not go down RAM write data when the RAM data read empty an empty sign, can not read data from RAM.
Platform: | Size: 333824 | Author: 肖波 | Hits:

[VHDL-FPGA-Verilog] ram_fifo

Description: Altera RAM FIFOIP核，实现对FIFO的读写，对满信号和空信号进行判断.-altera ram fifo ip core
Platform: | Size: 3232768 | Author: xuguo | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: FPGA内设计同步FIFO和异步FIFO，以及双口RAM的方法,FIFO设计的经验之谈，非常经典。-Synchronous FIFO and asynchronous FIFO, and dual-port RAM within the FPGA design,FIFO design rule of thumb, very classic.
Platform: | Size: 2388992 | Author: peter | Hits:

[VHDL-FPGA-Verilog] ram-and-fifo

Description: ALTERA公司的一些关于RAM，FIFO等IP核的技术文档，对用到IP核存储设备的读者很有用！-ALTERA Company RAM, FIFO IP core technical documentation, readers used IP core storage devices useful!
Platform: | Size: 920576 | Author: 刘宁 | Hits:

[VHDL-FPGA-Verilog] Synchronous-FIFO

Description: FIFO是英文FIRST-IN-FIRST-OUT的缩写，是一种先进先出的数据缓存器，它与普通存储器的区别是没有外部读写地址线，这样使用起来非常方便，但是缺点是只能顺序读写数据，其数据地址由内部读写指针自动加1完成 FIFO的主要功能是基于对双口RAM的读写控制来完成的，根据双口RAM的数据存储状况产生空满信号。双口RAM指的就是能同时对RAM进行读写操作的RAM存储器 -FIFO is an abbreviation of the English FIRST-IN-FIRST-OUT, which is a FIFO data buffer, it is the difference between ordinary memory is no external write address lines, so very convenient to use, but the drawback is that only the order read and write data, the data read by the internal address pointer is automatically incremented by 1 to complete the FIFO main function is based on the dual-port RAM read and write control to complete, resulting in empty status full signal based on data stored in the dual-port RAM. Refers to the dual-port RAM can simultaneously read and write RAM RAM memory
Platform: | Size: 4096 | Author: 刘东辉 | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
Platform: | Size: 10222592 | Author: 丶大娱乐家 | Hits:
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